1. Technical Field
The present disclosure relates to the field of semiconductor technology, and more particularly to a semiconductor device and manufacturing method thereof.
2. Description of the Related Art
In the field of semiconductor technology, for advanced complementary metal-oxide-semiconductor (CMOS) logic devices, stress engineering is one of the most important factors in improving device performance. For example, in a P-type metal-oxide-semiconductor (PMOS) device, the compressive stress on the channel can be increased by forming an epitaxial silicon germanium source and drain, thereby increasing carrier mobility.
During the fabrication of the device, ion implantation is typically performed on the source and drain regions of the PMOS. However, in some instances, the ion implantation can cause damage to the lattice arrangement of the embedded silicon germanium layer, which releases a significant amount of the compressive stress that is applied by the embedded silicon germanium layer onto the channel of the PMOS. The release of the compressive stress reduces carrier mobility, thereby lowering the performance of the PMOS device.